A memory device of this type has a number of memory cells, which are arranged between row and column lines. In some kind of memory device, each column line may be electrically floating when a chip is not selected. Particularly, the column lines of a MOS memory device come to have a negative potential when the potential of, for example, the semiconductor substrate changes. Thus, a memory device of this type may fail to operate at a high speed or it may operate erroneously.
A known mask ROM comprises memory cells, i.e. MOS FETs formed in a semiconductor substrate, row lines, column lines, a row decoder and a column decoder. The row decoder selects one of the row lines. Each memory cell is driven by voltage supplied through the row line to which it is connected. Of the memory cells, those which have their drains connected to the column lines store a binary value "0". The other memory cells which have their drains not connected to the column lines store a binary value "1". All these memory cells have their sources connected to a second voltage source i.e. ground. The column lines include transistors for selecting one of the column lines, respectively. The gates of these transistors are connected to the column decoder. The column decoder selects and drives one of the transistors included in the column lines. Further provided is a voltage sensing circuit for detecting which binary value, "0" or "1", the column line selected by the column decoder produces. The circuit delivers through an output circuit an output signal which represents which binary value has been produced by the column line selected. All the MOS transistors used in the mask ROM are of N-channel enhancement type. Power source voltage is higher than the ground potential.
In the mask ROM a chip is selected by a chip enable signal. The mask ROM consumes less power when a chip is not selected than when it is selected. To raise the speed with which data is read out from the ROM immediately after the ROM has been enabled by a chip enable signal and to reduce the power consumption, the following measures are taken commonly. That is, all the row lines of the ROM are charged through the row decoder at level "1" when chip is not selected. When a chip is enabled and one of the row lines is selected, all the other row lines are discharged.
FIG. 1 shows the coupling capacitances among the row lines, column lines, substrate and ground potential of the above-described mask ROM. In FIG. 1, C.sub.1 is coupling capacitance between a row line and column line, C.sub.2 coupling capacitance between a column line and the substrate, C.sub.3 coupling capacitance between a column line and the ground, C.sub.4 coupling capacitance between a row line and the substrate, and C.sub.5 coupling capacitance between the substrate and the ground. As evident from FIG. 1, the row lines have a coupling capacitance with respect to the column lines and the substrate Sub. If the column lines are electrically floating when chip is not selected or enabled, the column lines and the substrate Sub will have a negative potential due to the noise generated when all the row lines are discharged. Of course, the column lines and the substrate Sub will have a positive potential when the row lines are charged.
Further, if there is a power source noise, the potential of the substrate will vary. Such a potential variation changes the potential of the column lines which are electrically floating. Moreover, a potential variation of internal nodes (e.g. the row lines), if any, changes the potential of the column lines through the gates of the memory cells. Further, in an integrated circuit with three power sources in which a bias voltage is applied to the substrate, the potential of the column lines tends to drop to the potential of the substrate due to current leaking from the column lines or from the PN junctions of the drains of the memory cells when the column lines are not selected and electrically floating. Thus, when the potential of the column lines drops to "V.sub.G -V.sub.th ", where V.sub.G is the gate voltage of the transistors included in the column lines and V.sub.th is the threshold voltage thereof, the transistors are turned on whereby the column lines are held at a negative voltage lower than the source potential which is usually 0 volt.
In an EPROM (Erasable Programmable ROM) which is exposed to external light, the nodes (e.g. column lines) which are put in a floating state by the current generated in the PN junction by the external light will inevitably have their potential reduced to a negative potential which is lower than the potential of the substrate (usually 0 volt) by the forward voltage of the PN junction. If this happens, the column line which has been selected must be charged to have a higher potential than said negative potential, and such necessary charging of the selected column line will reduce the data-reading speed. If the substrate potential becomes a negative one, the capacitance among the column lines reduces the potential of all the unselected column lines to a negative potential. Thus, all the transistors for selecting the column lines, which have been in an off state, are rendered conductive. Through these transistors each column lines is charged. As a result, the data reading speed will be much reduced if data are read out under this condition.
If said charge phenomenon takes place right after the data reading, the potential of the selected column line is lowered. The potential of the input terminal, i.e. the "1" level, of the voltage sensing circuit will inevitably be detected erroneously as the "0" level, and the EPROM will operate erroneously. Consequently the EPROM will read out wrong data until the input terminal of the voltage sensing circuit is charged to the "1" level.
To avoid the above-mentioned unstable operation of a memory device, the column lines may be charged to the "1" level or a similar level as long as they are not selected. This method can indeed lessen the above-mentioned problems, but cannot be applied to, for example an EPROM which comprises MIS transistors having charge trapping centers. If the column lines of an EPROM are charged to the "1" level or a similar level, electrons will be injected erroneously into the charge trapping centers. This will render the EPROM alarmingly unreliable.